Processors
for computer vision
systems

ELISE processor
Multiplatform system-on-crystal
signal processor

Multiplatform System-on-a-Chip for computer vision systems
based on 28 nm process.

Orwell Processor

Orwell Processor

Designed for

IoT devices, smart cities, video analysis systems, retail, augmented reality, multimedia, security, transport infrastructure, communication devices, navigation devices, industrial electronics. ELISE processor is
a multiplatform System-on-a-Chip (SoC) based on
28nm process.

Functional capabilities

  • ELISE SoC comprises several processor cores used for execution of tasks of varying intensity, a set of IP-blocks for processing high definition video streams with stereo image support capability,
    an 8-core DSP cluster for video analysis tasks, a high-performance GPU
    and a multi-standard navigation core.
  • The chip is multifunctional and can be used for working with convolution neural networks or as the main processor for tablet PCs, PCs, air drones and other devices.

System Components:

  • 2 core MIPS Warrior P5607 - 1.2 GHz
  • 1 core of MIPS interAptiv - 1 GHz
  • 1 core MIPS M5150 - 600 MHz
  • Graphic controller PowerVR Clyde GX6250 - 2 600 MHz cores
  • 8-core DSP processor Velcore2 with support for video analytics algorithms
  • PowerVR E4500 Onyx video encoder, supported formats: H.264, MPEG-4, MPEG-2; 4 conveyors with 10 bits, data format 4: 2: 0/4: 2: 2/4: 4: 4; 3840x2160p30
  • Video decoder PowerVR D5500 Coral, supported formats: HEVC, H.264, MPEG-4, MPEG-2; 4 conveyors with 10 bits, data format 4: 2: 0/4: 2: 2/4: 4: 4; HEVC 3840x2160p60 / H264, 3840x2160p30
  • GNSS Multi-Channel Navigation Kernel: GLONASS / GPS / BeiDou / GALILEO

ORWELL Processor

Peripherals:

  • Ensigma C4250 (RPU) built-in radio modem that supports communication standards: IEEE 802.11ac 2x2 MIMO Wi-Fi (867 Mbps), 600 MHz Viterbi / LDPC, Bluetooth 4.1 Baseband
  • 2 ports MIPI CSI 2.0
  • 2 ports HiSPI
  • CMOS IF
  • HDMI 2.0 RX video input
  • 2 ports MIPI DSI 1.1
  • 2 HDMI 2.0 TX ports
  • FPD-Link (LVDS)
  • 2 PDP ports
  • 2 ports DDR4-2400
  • ONFI NAND Flash Controller
  • Ethernet 10/100/1000
  • 2 USB 3.0 / 2.0 ports
  • 3rd port of SD Host
  • 2 UART ports
  • 2 I2S ports
  • S/PDIF
  • 8 I2C ports
  • 2 SPI ports
  • 2 JTAG ports
  • 4 PWM ports
  • 32 GPIO outputs

ORWELL Processor

VIP-1 processor
Energy-efficient multicore

An advanced energy-efficient multicore signal microprocessor based on 40 nm process.

ORWELL Processor

ORWELL Processor

Designed for

Communication devices, navigation and mobile devices, smart video cameras, robotic systems, driver assistance systems, smartphones and other gadgets.

Functional capabilities

  • VIP-1 is a high-performance multifunctional microprocessor, which can serve as the main element for mobile devices, security systems and GLONASS trackers.
  • The System-on-a-Chip has an embedded custom video processor enabling video data processing, analysis and semantic processing.
  • The chip is a good choice for designing video cameras with embedded video analysis, as it is equipped with two DSP and VPU VELcore cores, and a MIPI interface.

System Components:

  • 2-core CPU CORTEX-A9 (CPU 0-1) with FPU-accelerator and NEON SIMD-accelerator (ARM);
  • 2 DSP core with floating and fixed point ELCore-30M; full software compatibility with microcircuits 1892VM10Я, 1892VM15F;
  • Graphical 2D/3D Accelerator (MALI- 300, ARM); support OpenVG 1.1, OpenGLES 2.0/1.1; Support for resolutions up to HD 1080p with 4x anti-aliasing; built-in 8 KB cache second level; 250 million pixels/s;
  • The core of a multichannel GLONASS / GPS / BeiDou-correlator;
  • VELcore-01 video codec: providing functions H.264 CBP Encode and Decode, FullHD (1920x1080) stereo video stream with frame rate not less than 30 frames per second, video data memory VRAM of 1 MB available for CPU and DSP;
  • Hardware Accelerator for compressing images in accordance with JPEG standard.

Peripherals:

  • Ethernet controller MAC 10/100/1000;
  • 2 ports LPDDR2 / DDR3; top speed data transmission 1008 Mbit/s at a frequency of 504 MHz; bit depth - 16/32;
  • NORMPORT port for connecting memory SRAM / PSRAM / ROM / NOR FLASH;
  • NANDMPORT port for connecting NAND FLASH memory;
  • 2 SD / MMC ports with support for SD3.0 / MMC4.5;
  • 2 multifunction ports MFBSP (LPORT, SPI, I2S, GPIO) with DMA;
  • 4 universal asynchronous ports (UART) type 16550A;
  • USB2.0 (HOST + DEVICE + PHY), 480 Mbps;
  • "Intelligent" multi-channel DMA SDMA controller;
  • DMA controller with direct PDMA peripheral request processing;
  • 128 multiplexed GPIO outputs; the ability to enter 2 external interrupts;
  • 3 I2C interface ports;
  • 2 dedicated SPI ports;
  • dedicated I2S interface port;
  • 2 two-channel PWM controllers;
  • 2 SpaceWire ports for network capabilities of the chip;
  • 8 universal 32-bit timers, interval/real time (IT/RTT);
  • 32-bit watchdog timer (WDT);
  • the real-time clock (RTC);
  • DAP debugging port with access to internal memory chip;

    2 video input ports:
    • a MIPI CSI port or a parallel port;
    • Built-in DMA;
    • built-in Image Preprocessor.

    Port of video data output:
    • port MIPI DSI or parallel port;
    • built-in DMA.
  • power management controller

ORWELL Processor

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